Subject description - B2M34PNIS

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B2M34PNIS Advanced Integrated System Design
Roles:PV Extent of teaching:2P+2C
Department:13134 Language of teaching:CS
Guarantors:Jakovenko J. Completion:Z,ZK
Lecturers:Jakovenko J. Credits:6
Tutors:Jakovenko J. Semester:Z

Anotation:

Students will gain advanced knowledge in analog and digital integrated circuit design. The subject itself deals with the hierarchical design of integrated circuits in BCD technologies compared to CMOS technologies. The subject further emphasizes good design practices, advanced building blocks in BCD technologies, advanced IP blocks and their design process. An integral part of the subject are topics focused on the design of power MOSFETs, Linear voltage regulators (LDO), electronic fuses eFUSE, switching power supplies on a chip (SMPS) digital Front-end (FE) and digital Back-end (BE) design and detailed analysis of layouts. The subject is dealt with further advanced error analysis methods, using analytical methods such as optical and electron microscopy, (Optical Beam Induced Resistance Change - Obirch and Emission Microscopy EmMi).

Content:

Students will gain advanced knowledge in analog and digital integrated circuit design. The subject itself deals with the hierarchical design of integrated circuits in BCD technologies compared to CMOS technologies. The subject further emphasizes good design practices, advanced building blocks in BCD technologies, advanced IP blocks and their design process. An integral part of the subject are topics focused on the design of power MOSFETs, Linear voltage regulators (LDO), electronic fuses eFUSE, switching power supplies on a chip (SMPS) digital Front-end (FE) and digital Back-end (BE) design and detailed analysis of layouts. The subject is dealt with further advanced error analysis methods, using analytical methods such as optical and electron microscopy, (Optical Beam Induced Resistance Change - Obirch and Emission Microscopy EmMi).

Course outlines:

Osnovy přednášek:
1. Birth of a new chip; hierarchy design, discrete vs. IC implementation, description of BCD technology.
2. Good design practices - Mirroring, cascoding, sizing/dimensioning, matching, current capability, Rdson,
Comon Mode+CASC, downscaling in digital vs analog, Grounding, accuracy analog ICs.
3. Advanced IC building blocks design - part I – Precise voltage and current reference, Advanced Configurable
Dividers, Mix mode circuits (ADC, DAC etc).
4. Advanced IC building blocks design - part II - Level shifter, Current sensor, Charge pump Oscillator, etc.
5. Advanced IP block block design - Linear voltage regulators (LDOs), eFUSE, Switched-mode power supply
(SMPS)
6. Advanced layout design flow - analog TOP, digital TOP; Layout dependent effects (WPE, STI, wSTI, ant. diode,
PID, metal stress); floorplan (top-bottom, bottom-top, noise IP, sensitive IP, pad position)
7. Chip as mine field: ESD protection, latch-up immunity, Trimming, Testability; Parasitic, Post Layout
Simulation, Tunings.
8. PWR MOSFETs design in analog circuits: drift, extended drain, voltage class
9. Digital IC design FE - part I: STA, clock tree, synthesis, implementation
10. Digital IC design FE + TOP level verification: behavioral models; AMS simulation, verification flow
11. Digital IC design BE - part I: Synthesis, Floor plan
12. Digital IC design BE - part II: Place and route, IR drop analysis, DRC, LVS
13. Bug analysis methods in IC design flow: Electrical measurement, reproduction, Optical, electron microscopy,
SAW, X-ray, IR, Obirch, LASER cut, FIB cut + deposition, Hypothesis, isolation, prove, metal fix
14. Reserver

Exercises outline:

1. BCD technology description, chip description follows, IPs in schematic and layout on the project,
2. Sizing and matching in advanced ICs, fingers vs. multiply transistor division.
3. Precise reference sources design (Voltage reference, Current reference, Divider)
4. How to design Advanced OpAmp, improved Miller OpAmps (by using telescope CM, cascode)
5. How to create a hierarchy in ICs (Ref.+OpAmp)
6. Advanced layout design practices of matched IP blocks – Part I 7. Advanced layout design practices of matched IP blocks – Part II + PLS
8. Power MOS layout (including metallization design)
9. Digital FE - part I: How to write RTL code with focus on synthesis and implementation into ASIC technology
process
10. Digital FE - part II: How to write RTL code with focus on synthesis and implementation into ASIC technology
process
11. Digital BE - part I: How to deal with advanced synthesis
12. Digital BE - part II: How to implement standard cells (placement and routing) or FPGA implementation
13. Digital BE - IR drop analysis, DRC, LVS
14. Project review

Literature:

Recommended references: Analog design:
1) Razavi: Design of Analog CMOS Integrated Circuits, McGRAW-Hill,
2) Murari, F. Bertotti, G.A.Vignola: Smart Power ICs, Springer,
3) Gray, P Hurst, s. Lewis, R. Mayer: Analysis and Design of Analog Integrated Circuits, John Wiley and Sons.
Analog design:
1) Analysis and Design of Analog Integrated Circuits, 5th Edition, by J. Paul R. Gray, Paul J. Hurst, Stephen H.
Lewis, Robert G. Meyer
2) Analog Integrated Circuit Design, by Tony Chan Carusone, David Johns, Kenneth Martin
Analog layout:
1) The Art of Analog Layout, by Alan Hastings
2) Fundamentals of Power Semiconductor Devices, by BJ Baliga
3) Analog-to-Digital Conversion, by Marcel J.M. Pelgrom
Digital design:
1) P. J. Ashenden, The Designer's Guide to VHDL, Morgan Kaufmann, 2008

Requirements:

Subject is included into these academic programs:

Program Branch Role Recommended semester
MPEK1_2018 Electronics PV 3


Page updated 23.7.2024 17:51:35, semester: Z,L/2023-4, Z,L/2024-5, Send comments about the content to the Administrators of the Academic Programs Proposal and Realization: I. Halaška (K336), J. Novák (K336)