Subject description - ANI-SIME

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ANI-SIME Digital Circuit Simulation and Verification
Roles:PV Extent of teaching:2P+1C
Department:18103 Language of teaching:CS
Guarantors:Kohlík M. Completion:Z,ZK
Lecturers:Kohlík M. Credits:6
Tutors:Kohlík M. Semester:Z

Web page:

https://courses.fit.cvut.cz/NI-SIM/

Anotation:

The aim of the course is to acquaint the students with principles of digital circuit simulation at RTL (Register Transfer Level) and TLM (Transaction Level Modeling) levels and with the properties of proper tools. The course covers recent verification methods, too.

Study targets:

The goal of the course is to acquaint students with the properties of the above-mentioned languages and their use for verification (simulation).

Content:

The aim of the course is to acquaint the students with principles of digital circuit simulation at RTL (Register Transfer Level) and TLM (Transaction Level Modeling) levels and with the properties of proper tools. The course covers recent verification methods, too.

Course outlines:

1. Fundamental simulation and verification principles.
2. Simulation languages VHDL and Verilog.
3. Sequential and paralel simulation environment.
4. Hierarchical structure specification, parametrization.
5. Functions, procedures, and events in simulation models.
6. Design checking, using of assertions.
7. Verilog/SystemVerilog: introduction, data types, comparisons.
8. Communication between modules, transactions.
9. Simulation management, random and delimited stimulus generation, coverage control.
10. Advanced design control in simulation, assertion in SystemVerilog.
11. Universal Verification Methodology (UVM).
12. Advanced constructions, register model.

Exercises outline:

1. Introduction, VHDL/Verilog project - Assignment.
2. VHDL/Verilog project - Consultation.
3. VHDL/Verilog project - Evaluation.
4. Test 1 - VHDL/Verilog, Verilog/SystemVerilog project - Assignment.
5. Verilog/SystemVerilog project - Consultation.
6. Test 2 - Verilog/SystemVerilog, Verilog/SystemVerilog project - Evaluation.

Literature:

Mehta, A. B. : SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications. Springer, 2016. ISBN 9783319305394. Mehta, A. B. : ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. Springer, 2018. ISBN 9783319594187. Mehler, R. : Digital Integrated Circuit Design Using Verilog and Systemverilog (1st Edition). Elsevier, 2014. ISBN 9780124095298. Cohen, B. - Kumari, S. V. A. - Piper, L. : SystemVerilog Assertions Handbook (3rd Edition). VhdlCohen Publishing, 2013. ISBN 978-0-9705394-3-6.

Requirements:

Design methods for combinational and sequential logic circuits, knowledge of number representations, and knowledge of the circuit implementations of basic arithmetic operations.

Keywords:

Module, interface, signal, delta delay, resolution function, inertial and transport delay, sequential environment, parallel environment, behavioral description, structural description, transaction level modeling, assertions, parallel simulation.

Subject is included into these academic programs:

Program Branch Role Recommended semester
MPEIS_2026 Common courses PV 1

Page updated 16.6.2026 17:52:00, semester: L/2029-30, Z,L/2027-8, L/2028-9, Z,L/2026-7, Z/2028-9, L/2025-6, Send comments about the content to the Administrators of the Academic Programs Proposal and Realization: I. Halaška (K336), J. Novák (K336)
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